this document is a general product description and is subject to change without notice. hynix semiconductor does not assume any responsibility for use of circuits described. no patent licenses are implied. rev.0 5 / dec . 2000 hynix semiconductor hy62 s f16 2 0 1a series 128 kx16bit full cmos sram document title 128k x16 bit 1.8v super low power full cmos slow sram revision history revision no history d raft date remark 05 divide output load into two factors dec.10. 2000 final - tclz,tolz,tblz,tchz,tohz,tbhz,twhz,tow - others add ma rking information
hy62 s f16201a rev.0 5 / dec . 2000 2 description the hy62 s f16201a is a high speed, low power and 2 m bit full cmos sram organized as 131,072 words by 16bit. the hy62 s f1620 1 a uses high performance full cmos process technology and designed for high speed low power circuit technology. it is particularly well suited for used in high density low power system application. this device has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 1.2 v. features fully static operation and tri - state output ttl compatible inputs and outputs battery backup(ll - part) - . 1.2v(min) data retention standard pin configuration - . 48 - f bga product voltage speed operation standby current(ua) temperature no. (v) (ns) current /icc (ma) ll sl ( c ) hy62 s f16201a 1.7~2.3v 85 /1 0 0/1 2 0 3 3 1 0~70 hy62 s f16201a - i 1.7~2.3v 85 /1 0 0/1 2 0 3 3 1 - 40~85( i ) note s : 1. blank : commercial, i : industrial 2. current value is max. pin connection block diagram /lb io9 io10 /oe a0 a1 a2 nc /ub a3 a4 /cs io1 io11 a5 a6 io2 io3 vss io12 nc a7 io4 vcc vcc io13 nc a16 io5 vss io15 io14 a14 a15 io6 io7 io16 nc a12 a13 /we io8 nc a8 a9 a10 a11 nc 48 - fbga(top view) pin description pin name pin fun c tion pin name pin fun c tion /cs chip select i/o1~i/o16 data input s / outpu t s /we write enable a0~a1 6 address input s /oe output enable vcc power( 1.7v ~ 2.3 v ) /lb low er byte control(i/o1~i/o8) vss ground /ub upper byte control(i/o9~i/o16) nc no connection memory array 128k x 16 row decoder sense amp write driver data i/o buffer i/o1 i/o16 columndecoder contro llogic add input buffer a0 a16 /cs /oe /lb /ub /we
hy62 s f16201a rev.0 5 / dec . 2000 2 ordering information part no. speed power temp. package hy62 s f16201all f 85/ 100/120 ll - part fbga hy62 s f16201all f 85/ 100/120 s l - part fbga hy62 s f16201all f - i 85/ 100/120 ll - part i fbga hy62 s f16201all f - i 85/ 100/120 s l - part i fbga note : 1 . blank : commercial, i : industrial absolute maximum rating (1) symbol parameter rating unit remark v in, v out input/output voltage - 0.2 to 3.6 v vcc power supply - 0. 2 to 4. 6 v t a operating temperature 0 to 70 c hy62 s f1620 1 a - 40 to 85 c hy62 s f1620 1 a - i t stg storage temperature - 55 to 150 c p d power dissipation 1.0 w t solder ball soldering temperature & time 260 10 c sec note : 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. exposure to the absolute maximum rating conditions for extended period may affect reliability. tru th table i/o /cs /we /oe /lb /ub mode i/o1~i/o8 i/o9~i/o16 power h x x x x des elected hi gh - z hi gh - z standby x x x h h deselected hi gh - z hi gh - z standby l h h l x output disabled hi gh - z hi gh - z active l h h x l output disabled hi gh - z hi gh - z acti ve l h l l h read d out hi gh - z active h l hi gh - z d out l l d out d out l l x l h write d in hi gh - z active h l hi gh - z d in l l d in d in note : 1. h=v ih , l=v il , x=don't care 2. ub, lb(upper, lower byte enable) these active low inputs allow individual bytes to be written or read. when lb is low, data is written or read to the lower byte, i/o 1 - i/o 8. when ub is low, data is written or read to the upper byte, i/o 9 - i/o 16.
hy62 s f16201a rev.0 5 / dec . 2000 3 recommended dc operating condition symbol pa rameter min. typ. max. unit vcc supply voltage 1. 7 1.8 2. 3 v vss ground 0 0 0 v v ih input high voltage 1. 4 - vcc+0. 3 v v il input low voltage - 0. 3 (1) - 0.4 v note : 1. vil = - 1.5v for pulse width less than 30ns 2. typical values is not 100% tested dc electrical characteristics vcc = 1. 7 v ~ 2.3v , t a = 0 c to 70 c/ - 40 c to 85 c ( i ) sym bol parameter test condition min . typ . max . unit i li input leakage current vss < v in < vcc - 1 - 1 ua i lo output leakage current vss < v out < vcc, /cs = v ih or / oe = v ih or /we = v il , / ub = /lb = v ih - 1 - 1 ua icc operating power supply current /cs = v il , v in = v ih or v il , i i/o = 0ma - - 3 ma cycle time = min.100% duty, /cs = v i l, v in = v ih or v il , i i/o = 0ma , - - 20 m a i cc1 average operating current cycle time = 1u s, /cs < 0.2 v, v in <0.2v, i i/o = 0ma , 3 m a i sb standby current (ttl input) /cs = v ih or /ub = /lb = v ih , v in = v ih or v il - - 0.15 ma sl - - 1 ua i sb1 standby current (cmos input) /cs > vcc - 0.2v or /ub = /lb > vcc - 0.2v, v in > vcc - 0.2 v or ll - 0.5 3 ua v in < vss + 0.2v v ol output low voltage i ol = 0.1 ma - - 0. 2 v v oh output high voltage i oh = - 0.1 ma 1.6 - - v note s : 1. typical values are at vcc = 1.8 v, t a = 25 c 2. typical values are sampled and not 100% tested capacita nce (temp = 25 c , f= 1.0mhz) symbol parameter condition max. unit c in input capacitance(add, /cs, /we, /ub, /lb, /oe) v in = 0v 8 pf c out output capacitance(i/o) v i/o = 0v 10 pf note : 1. these parameters are sampled and not 100% tested
hy62 s f16201a rev.0 5 / dec . 2000 4 ac c haracteristics vcc = 1.7v~2.3v, t a = 0 c to 70 c/ - 40 c to 85 c (i), unles s otherwise specified - 85 - 10 - 12 # symbol parameter min. max. min. max. min . max. read cycle 1 trc read cycle time 85 - 100 - 120 - ns 2 taa address access time - 85 - 100 - 120 ns 3 tacs chip select access time - 85 - 100 - 120 ns 4 toe output enable to output valid - 4 0 - 50 - 60 ns 5 tba /lb, /ub access time - 85 - 100 - 120 ns 6 tclz chip select to output in low z 10 - 20 - 20 - ns 7 tolz output enable to output in low z 5 - 5 - 10 - ns 8 tblz /lb, /ub enable to output in low z 5 - 5 - 10 - ns 9 tchz chip deselection to output in high z 0 30 0 30 0 40 ns 10 tohz out disable to output in high z 0 30 0 30 0 40 ns 11 tbhz /lb, /ub disable to output in high z 0 30 0 30 0 40 ns 12 toh output hold from address change 10 - 15 - 15 - ns write cycle 13 twc write cycle time 85 - 100 - 120 - ns 14 tcw chip selection to end of write 70 - 80 - 100 - ns 15 taw address valid to end of write 70 - 80 - 100 - ns 16 tbw /lb, /ub valid to end of write 70 - 80 - 100 - ns 17 tas address set - up time 0 - 0 - 0 - ns 18 twp write pulse width 55 - 75 - 85 - ns 19 twr write recovery time 0 - 0 - 0 - ns 20 twhz write to output in high z 0 30 0 35 0 40 ns 21 tdw dat a to write time overlap 35 - 45 - 50 - ns 22 tdh data hold from write time 0 - 0 - 0 - ns 23 tow output active from end of write 5 - 10 - 10 - ns ac test conditions t a = 0 c to 70 c ( normal ) / - 40 c to 85 c (i), unless otherwise specified parameter v alue input pulse level 0.4v to 1. 6 v input rise and fall time 5ns input and output timing reference level 0.9v tclz,tolz,tblz,tchz,tohz,tbhz,twhz,tow cl = 5pf + 1ttl load output load others cl = 30pf + 1ttl load ac test loads d out 3273 ohm cl(1) 4091 ohm v tm = 1.7v note : 1 . including jig and scope capacitance unit
hy62 s f16201a rev.0 5 / dec . 2000 5 timing diagram read cycle 1( n ote 1,4 ) read cycle 2(note 2 , 3 ,4) addr data out trc taa data valid previous data toh toh read cycle 3(note 1,2 ,4) /cs /ub, /lb data out tacs data valid tclz(3) tchz(3) notes: a r ead occurs during the overlap of a low /oe, a high /we, a low /cs1 and low /ub and / or /lb . 2. /oe = v il 3. transition is measured + 200mv from steady state voltage. this parameter is sampled and not 100% tested. 4. /cs in high for the standby, low for active /ub and /lb in high for the standby, low for active addr trc / cs taa tacs toh data valid high - z data out / ub ,/ lb / oe tba toe tclz (3) tblz (3) t olz (3) t chz (3) t bhz (3) tohz (3)
hy62 s f16201a rev.0 5 / dec . 2000 6 write cycle 1 (1,4,8) (/we controlled) write cycle 2 ( 1,4,8 ) (/cs controlled) notes: 1. a write occurs during the overlap o f a low /we, a low /cs1 and low /ub and/or /lb. 2. twr is measured from the earlier of /cs, /lb, /ub, or /we going high to the end of write cycle. 3. during this period, i/o pins are in the output state so that the input signals of opposite phase to the output must not be applied. 4. if the /cs, /lb and /ub low transition occur simultaneously with the /we low transition or after the /we transition, outputs remain in a high impedance state. 5 . q(data out) is the same phase with the write data of this write cycle. 6. q(data out) is the read data of the next address. 7. transition is measured +200mv from steady state. this parameter is sampled and not 100% tested. 8 . /cs in high for the standby, low for active /ub and /lb in high for the st andby, low for active data valid addr data out / cs / ub , / lb / we twc tcw twr (2) tbw taw twp data in high - z tas twhz (3, 7 ) t dw tdh tow ( 5 ) ( 6 ) data valid addr data out / cs / ub , / lb / we twc tcw twr (2) tbw taw twp data in tdw tdh high - z high - z tas
hy62 s f16201a rev.0 5 / dec . 2000 7 data retention electric characteristic t a = 0 c to 70 c / - 40 c to 85 c (i) symbol parameter test condition min . typ . max . unit v dr vcc for data retention /cs > vcc - 0.2v or /ub = /lb > vcc - 0.2v, 1. 2 - 2.3 v v in > vcc - 0.2v or v in < vss + 0.2v i ccdr data retention current vcc=1.5v, /cs > vcc - 0.2v or /ub = /lb > vcc - 0.2v, ll - - 3 ua v in > vcc - 0.2v or sl - - 1 ua v in < vss + 0.2v tcdr chip deselect to data retention time see data retention timing dia gram 0 - - ns tr operating recovery time trc ( 3 ) - - ns notes: 1. typical values are under the condition of t a = 25 c . 2. typical values are sampled and not 100% tested 3 . trc is read cycle time. data retention timing diagram cs vdr cs > vcc-0.2v tcdr tr vss vcc 1.7v data retention mode or /ub &/lb or /ub = /lb > vcc ? 0.2v
hy62 s f16201a rev.0 5 / dec . 2000 8 p ackage information 48ball fine pitch ball grid array package( f ) bottom view top view b a a1 corner b1/2 index area 6 5 4 3 2 1 a a b c d c c1 e f g c1/2 c1/2 h b1/2 b1 side view 5 e1 e2 c e seating plane 4 a r 3 d(diameter) symbol min. typ. max. a - 0.75 - b - 3.75 - b1 6.9 7.0 7.1 c - 5.25 - c1 7.9 8.0 8.1 d 0.3 0.35 0.4 e - 1.0 1.1 e1 0. 74 0. 78 0. 82 e2 0.17 0.2 2 0. 27 r - - 0.08 note 1. dimensioning and tolerancing per asme y14. 5 m - 1994. 2. all dimensions are millimeters. 3. dimension ?d? is measured at the maxi mum solder ball diameter in a plane parallel to datum c. 4. primary datum c(seating plane) is defined by the crown of the solder balls. 5 . this is a controlling dimension.
hy62 s f16201a rev.0 5 / dec . 2000 9 marking instruction package marking example h y s f 6 2 1 a c s s t y y w w p x x x x x k o r fbga index ? hysf621ac : part name c : power consumption - l : low low power - s : super low power ? ss : speed - 85 : 85ns - 10 : 100ns - 12 : 120ns ? t : temperature - c : industrial ( -0 ~ 70 c ) - i : industrial ( -40 ~ 85 c ) ? yy : year (ex : 00 = year 2000, 01= year 2001) ? ww : work week ( ex : 12 = work week 12 ) ? p : process code ? xxxxx : lot no. ? kor : origin country note - capital letter : fixed item - small letter : non-fixed item
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